Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices-Reference-Cited by-同舟云学术

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Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices

Published:2013-10 Issue:10 Volume:60 Page:2549-2560
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Ker Ming-Dou,Chiu Po-Yen

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/6609087/06609128.pdf?arnumber=6609128

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. 3.2 Gbps Output Driver With Dual Low Voltage Modes and Low Power PVT Compensation Circuit;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process;Integration;2023-05

4. A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique;IET Circuits, Devices & Systems;2022-10-30

5. A CMOS On-Chip High-Precision PVTL Detector;Advances in Science, Technology and Engineering Systems Journal;2022-05

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