3.2 Gbps Output Driver With Dual Low Voltage Modes and Low Power PVT Compensation Circuit
Author:
Affiliation:
1. National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181504.pdf?arnumber=10181504
Reference8 articles.
1. A $\hbox{Gb/s}+$ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time
2. A 2.5-GHz 2xVDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment;lee;2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS),0
3. A 90-nm 640 MHz 2xVDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compen-sation;wang;IEEE Trans Circuits Syst II Exp Briefs (TCAS-II),2020
4. A 90-nm CMOS 800 MHz 2 $$\times$$ × VDD output buffer with leakage detection and output current self-adjustment
5. 23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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