23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power-Reference-Cited by-同舟云学术

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Ha Kyung-Soo,Lee Chang-Kyo,Lee Dongkeon,Moon Daesik,Jang Jin-Hun,Hwang Hyong-Ryol,Chi Hyungjoon,Park Junghwan,Shin Seungjun,Park Dukha,Kim Sang-Yun,Lim Sukhyun,Park Kiwon,Choi YeonKyu,Kim Young-Hwa,Son Younghoon,Cho Hyunyoon,Na Byongwook,Ahn Hyo-Joo,Lee Seungseob,Choi Seouk-Kyu,Park Youn-Sik,Hyun Seok-Hun,Chang Soobong,Kwon Hyuck-Joon,Choi Jung-Hwan,Oh Tae-Young,Sohn Young-Soo,Park Kwang-II,Jang Seong-Jin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662509.pdf?arnumber=8662509

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