A $\hbox{Gb/s}+$ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8920/5420300/05420307.pdf?arnumber=5420307
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1. A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. 3.2 Gbps Output Driver With Dual Low Voltage Modes and Low Power PVT Compensation Circuit;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique;IET Circuits, Devices & Systems;2022-10-30
4. A CMOS On-Chip High-Precision PVTL Detector;Advances in Science, Technology and Engineering Systems Journal;2022-05
5. Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-02
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