A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique
Author:
Affiliation:
1. The School of Electronic and Information Engineering and the School of Microelectronics Xi'an Jiaotong University Xi'an China
2. The School of Microelectronics Southern University of Science and Technology Shenzhen China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/cds2.12133
Reference19 articles.
1. Monteiro R. Borges B. Anunciada V.:EMI reduction by optimizing the output voltage rise time and fail time in high‐frequency soft‐switching converters. In:2004 IEEE 35th Annual Power Electronics Specialists Conf. Aachen Germany vol.2 pp.1127–1132(2004)
2. Bazes M.:Output buffer impedance control and noise reduction using a speed‐locked loop. In:2004 IEEE Int. Solid‐State Circuits Conf. San Francisco CA vol.1 pp.486–541(2004)
3. A Slew Controlled LVDS Output Driver Circuit in 0.18 $\mu$m CMOS Technology
4. A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer
5. A Slew Rate Variation Compensated $2\times$ VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method
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