A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer

Author:

Lee Tzung-Je,Tsai Tsung-Yi,Lin Wei,Chio U-Fat,Wang Chua-ChinORCID

Funder

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

3. A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique;IET Circuits, Devices & Systems;2022-10-30

4. A CMOS On-Chip High-Precision PVTL Detector;Advances in Science, Technology and Engineering Systems Journal;2022-05

5. Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-02

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