A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process-Reference-Cited by-同舟云学术

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A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

Published:2023-11-19 Issue: Volume: Page:271-275
ISSN:
Container-title:2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
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Author:

Ke Jhih-Ying¹,Santos Tolentino Lean Karlo¹,Lo Cheng-Yao¹,Lee Tzung-Je¹,Wang Chua-Chin¹

Affiliation:

1. National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10509846/10509868/10509932.pdf?arnumber=10509932

Reference15 articles.

1. A nano-scale 2×VDD I/O buffer with encoded PV compensation technique

2. A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above

3. A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with low PVT Variation

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

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