A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/6609087/06595637.pdf?arnumber=6595637
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison;Electronics;2021-06-09
2. Passive element free variation aware decision circuit for 40 Gb/s CDR application;Microsystem Technologies;2019-11-07
3. An improved current mode logic latch for high-speed applications;International Journal of Communication Systems;2019-07-29
4. Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-03
5. Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-12
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