Passive element free variation aware decision circuit for 40 Gb/s CDR application

Author:

Maiti Madhusudan,Paul Anupama,Saw Suraj Kumar,Majumder AlakORCID

Funder

Ministry of Electronics and Information technology

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference27 articles.

1. Alioto M, Palumbo G (2006) Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework. IEEE Circ Syst Mag New Ser 6(4):40–59

2. Amamiya Y et al (2005) Low supply voltage operation of over 40 Gb/s digital Ics on parallel current switching latch circuitry. IEEE J Solid State Circ 40:2111–2117

3. Bespalko RD (2007) Transimpedance amplifier design using 0.18 um CMOS technology. MS Thesis, Queen’s University

4. Bonneau DP, Hauviller P, Vallet V (2007) Serializer/deserializer circuit for jitter sensitivity characterization. U.S. Patent No. 7,251,764

5. Chalvatzis T et al (2006) A 40-Gb/s decision circuit in 90-nm CMOS. Solid-State Circuits Conference, 2006. ESSCIRC 2006. In: Proceedings of the 32nd European. IEEE, 2006

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