An improved current mode logic latch for high-speed applications-Reference-Cited by-同舟云学术

An improved current mode logic latch for high-speed applications

Published:2019-07-29 Issue:13 Volume:33 Page:e4118
ISSN:1074-5351
Container-title:International Journal of Communication Systems
language:en
Short-container-title:Int J Commun Syst

Author:

Kumawat Mahesh¹^ORCID,Upadhyay Abhishek Kumar¹,Sharma Sanjay¹,Kumar Ravi¹,Singh Gaurav¹,Vishvakarma Santosh Kumar¹

Affiliation:

1. Discipline of Electrical Engineering, IIT; Indore India

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/dac.4118/fullpdf

Reference26 articles.

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2. Safwat S Hussein EE Ghoneima M Ismail Y A 12Gbps all digital low power SerDes transceiver for on-chip networking IEEE International Symposium on Circuits and Systems (ISCAS), 2011 https://doi.org/10.1109/ISCAS.2011.5937839

3. Hussein EE Safwat S Ghoneima M Ismail Y A 16Gbps low power self-timed SerDes transceiver for multi-core communication IEEE International Symposium on Circuits and Systems (ISCAS) 2012 https://doi.org/10.1109/ISCAS.2012.6271576

4. Singh N Deb S Analysis and design guidelines for customized logic families in CMOS Int. Symp , 2015 , 1 2 https://doi.org/10.1109/ISVDAT.2015.7208133

5. Green M. M Singh U. Design of CMOS CML circuits for high speed broadband communications In Proceedings of the International Symposium on Circuits and Systems , 2003 204 207

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