Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes-Reference-Cited by-同舟云学术

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Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes

Published:2014-09 Issue: Volume: Page:
ISSN:
Container-title:2014 27th IEEE International System-on-Chip Conference (SOCC)
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Author:

Jaiswal Ashok,walk Dominik,Fang Yuan,Hofmann Klaus

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6937053/6948870/06948891.pdf?arnumber=6948891

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Means to Accelerate Transfer of Information Between Integrated Circuits;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

2. PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-08

3. A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application;Journal of Circuits, Systems and Computers;2019-09-06

4. An improved current mode logic latch for high-speed applications;International Journal of Communication Systems;2019-07-29

5. Wave Combining Driver Based Serial Data Link Transceiver Design for Multi-Standard Applications;Journal of Nanoelectronics and Optoelectronics;2019-05-01

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