A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application

Abstract

In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32[Formula: see text]mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.