An active inductor employed CML latch for high speed integrated circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-022-02070-7.pdf
Reference34 articles.
1. Scotti, G., Bellizia, D., Trifiletti, A., & Palumbo, G. (2017). Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(12), 3509–3520. https://doi.org/10.1109/TVLSI.2017.2750207.
2. Kao, M., Wu, J., Chen, F., Chiu, C., & Hsu, S. S. H. (2009). A 10-Gb/s CML I/o circuit for backplane interconnection in 0.18-$$\mu $$m CMOS technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(5), 688–696. https://doi.org/10.1109/TVLSI.2009.2016726.
3. Damghanian, Masumeh, & Azhari, Seyed. (2017). A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications. Integration, the VLSI Journal. https://doi.org/10.1016/j.vlsi.2017.01.006.
4. Bommalingaiahnapallya, S., Sham, K., Ahmadi, M. & Harjani, R. (2007) High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator, In IEEE International Symposium on Circuits and Systems, pp. 3896–3899.https://doi.org/10.1109/ISCAS.2007.377890.
5. Shu, G., et al. (2016). A 4–10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition. IEEE Journal of Solid-State Circuits, 51(2), 428–439. https://doi.org/10.1109/JSSC.2015.2497963.
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