A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications

Author:

Damghanian Masumeh,Azhari Seyed Javad

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology;International Journal of Electronics and Telecommunications;2023-07-26

2. An active inductor employed CML latch for high speed integrated circuits;Analog Integrated Circuits and Signal Processing;2022-08-03

3. On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates;Microprocessors and Microsystems;2022-04

4. A new realization scheme for dynamic PFSCL style;Integration;2020-11

5. A Novel High-Performance ADC Flash Based on Bulk-Driven Quasi-Floating Gate Current Mirror;2020 17th International Multi-Conference on Systems, Signals & Devices (SSD);2020-07-20

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