High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations-Reference-Cited by-同舟云学术

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High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

Published:2015-01 Issue:1 Volume:62 Page:110-119
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Xie Jiafeng,Meher Pramod Kumar,Mao Zhi-Hong

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7001724/06914617.pdf?arnumber=6914617

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3. Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm;2018 IEEE 36th International Conference on Computer Design (ICCD);2018-10

4. Electrical-Spin Transduction for CMOS-Spintronic Interface and Long-Range Interconnects;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2017-12

5. A Fully Serial-In Parallel-Out Digit-Level Finite Field Multiplier in $\mathbb {F}_{2^{m}}$ Using Redundant Representation;IEEE Transactions on Circuits and Systems II: Express Briefs;2017-11

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