Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm

Author:

Lee Chiou-Yng,Xie Jiafeng

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m );IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

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3. Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction Techniques;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

4. Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-10

5. Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

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