Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10261320/10214411.pdf?arnumber=10214411
Reference39 articles.
1. A public-key cryptographic processor for RSA and ECC
2. An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic
3. High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA
4. Some new results on binary polynomial multiplication
5. Hardware design and implementation of ECC based crypto processor for low-area-applications on FPGA
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2. A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m );IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08
3. HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2 n ) Polynomial;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08
4. An Optimized VLSI Implementation of the Least Mean Square (LMS) Adaptive Filter Architecture on the Basis of Distributed Arithmetic Approach;Journal of The Institution of Engineers (India): Series B;2024-03-15
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