An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada
Funder
Windsor-Essex Economic Development Corporation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/9761844/09714068.pdf?arnumber=9714068
Reference42 articles.
1. Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication
2. Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2 m ) for Irreducible Polynomials
3. Binary Field Point Multiplication Implementation in FPGA Hardware
4. Fast Hybrid Karatsuba Multiplier for Type II Pentanomials
5. N-Term Karatsuba Algorithm and its Application to Multiplier Designs for Special Trinomials
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