An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic

Author:

Thirumoorthi Madhan1ORCID,Heidarpur Moslem1ORCID,Mirhassani Mitra1ORCID,Khalid Mohammed1ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada

Funder

Windsor-Essex Economic Development Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m );IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

2. HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2 n ) Polynomial;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

3. VLSI Implementation of Modified Karatsuba Multiplier for Low Power Applications;2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC);2024-06-28

4. Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

5. Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction Techniques;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

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