In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers
Author:
Funder
Università di Catania
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/8922968/08821561.pdf?arnumber=8821561
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
2. Stability and Figure of Merit Considerations in the Design of Three Stage CMOS Amplifiers;2023 International Symposium on Signals, Circuits and Systems (ISSCS);2023-07-13
3. Design and Implementation of Multi-Channel Readout Circuits for Low-Temperature Environments;Electronics;2023-05-04
4. Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-12
5. Design of voltage and current controller parameters using small signal model-based pole-zero cancellation method for improved transient response in microgrids;SN Applied Sciences;2021-10-09
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