Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/8453271/08319905.pdf?arnumber=8319905
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-10
2. Power and area optimized adaptive Viterbi decoder for high speed communication applications;International Journal of Information Technology;2022-08-22
3. Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems;Journal of Circuits, Systems and Computers;2021-12-08
4. Trellis coded modulation;Algorithms for Communications Systems and their Applications;2021-01-22
5. Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles;Journal of Electronic Testing;2020-06
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