An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/8453271/08345766.pdf?arnumber=8345766
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. Power and area optimized adaptive Viterbi decoder for high speed communication applications;International Journal of Information Technology;2022-08-22
4. Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems;Journal of Circuits, Systems and Computers;2021-12-08
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