Fast and Scalable Gate-Level Simulation in Massively Parallel Systems-Reference-Cited by-同舟云学术

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Fast and Scalable Gate-Level Simulation in Massively Parallel Systems

Published:2023-10-28 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
language:
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Author:

Hu Haichuan¹,Xu Zichen²,Wang Yuhao²,Liu Fangming¹

Affiliation:

1. National Engineering Research Center for Big Data Technology and System, School of Computer Science and Technology, Huazhong University of Science and Technology,Services Computing Technology and System Lab, Cluster and Grid Computing Lab,Wuhan,China,430074

2. School of Mathematics and Computer Science, Nanchang University,Nanchang,China

Funder

National Key R&D Program of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10323590/10323543/10323959.pdf?arnumber=10323959

Reference32 articles.

1. Iwls 2005 benchmarks;albrecht;International Workshop for Logic Synthesis (IWLS),2005

2. DTM Generation from LIDAR Data using Skewness Balancing

3. Circuit-gnn: Graph neural networks for distributed circuit design;zhang;International Conference on Machine Learning,0

4. Electrical Networks and Algebraic Graph Theory: Models, Properties, and Applications

5. GPU-based Hybrid Parallel Logic Simulation for Scan Patterns

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