An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator-Reference-Cited by-同舟云学术

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An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

Published:2014-04 Issue:4 Volume:61 Page:1133-1143
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Tsoumanis Kostas,Xydis Sotiris,Efstathiou Constantinos,Moschopoulos Nikos,Pekmestzi Kiamal

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/6777988/06710220.pdf?arnumber=6710220

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach;IETE Journal of Education;2023-05-29

2. Exact and approximate multiplications for signal processing applications;Microelectronics Journal;2023-02

3. FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation;IEEE Transactions on Circuits and Systems II: Express Briefs;2023

4. A Performance Comparison Review of Multiplier Designs;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02

5. Vedic Multiplier for High-Speed Applications;Communication, Software and Networks;2022-10-28

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