FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation-Reference-Cited by-同舟云学术

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FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation

Published:2023 Issue: Volume: Page:1-1
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Wang Yu¹,Liang Xingcheng²,Niu Shuai²^ORCID,Zhang Chi²,Lyu Fei²^ORCID,Luo Yuanyong³^ORCID

Affiliation:

1. School of Electronics Engineering, Nanjing Xiaozhuang University, Nanjing, China

2. School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China

3. Linx Lab, Department of Turing Architecture Design, HiSilicon, Huawei Corporation, Shenzhen, China

Funder

Scientific Research Foundation for the High-Level Talents of Jinling Institute of Technology

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/4358609/10227367.pdf?arnumber=10227367

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