Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach
Author:
Affiliation:
1. Department of Electronics and Communication Engineering, PES University, Bengaluru, India
2. Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bengaluru, India
Publisher
Informa UK Limited
Subject
General Earth and Planetary Sciences,General Engineering,General Environmental Science
Link
https://www.tandfonline.com/doi/pdf/10.1080/09747338.2023.2214514
Reference45 articles.
1. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator
2. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
3. High Speed Speculative Multipliers Based on Speculative Carry-Save Tree
4. Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder
5. Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator
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