A static low-power, high-performance 32-bit carry skip adder-Reference-Cited by-同舟云学术

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A static low-power, high-performance 32-bit carry skip adder

Published:2004 Issue: Volume: Page:
ISSN:
Container-title:Euromicro Symposium on Digital System Design, 2004. DSD 2004.
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Author:

Chirca K.,Schulte M.,Glossner J.,Horan Wang ,Mamidi B.,Balzola P.,Vassiliadis S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/9267/29440/01333335.pdf?arnumber=1333335

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Specific Investigations Concerning the Improveable Multiplier Architecture of High-Speed and Area-Efficient Adders;International Journal of Advanced Research in Science, Communication and Technology;2024-07-14

2. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08

3. Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation;El-Cezeri Fen ve Mühendislik Dergisi;2022-12-07

4. High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic;Journal of Circuits, Systems and Computers;2022-04-08

5. Certain Investigations on Adder Design for VLSI Signal Processing;2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS);2022-03-25

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