Author:
Yeh C.,Wilke G.,Chen H.,Reddy S.,Nguyen H.,Miyoshi T.,Walker W.,Murgai R.
Cited by
6 articles.
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1. Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18
2. Shift Power Reduction in High-Performance Clock Network Designs;2024 IEEE 8th International Test Conference India (ITC India);2024-07-21
3. Block Level Implementation Of Orca Top Using H-Technique;2023 International Conference on Computer Communication and Informatics (ICCCI);2023-01-23
4. Exploiting cache locality to speedup register clustering;Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17;2017
5. Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks;Integration;2013-09