Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks-Reference-Cited by-同舟云学术

Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

Published:2013-09 Issue:4 Volume:46 Page:382-391
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Abdelhadi Ameer,Ginosar Ran,Kolodny Avinoam,Friedman Eby G.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference27 articles.

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3. T. Xanthopoulos et al., The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor, in: Proceedings of the IEEE International Solid-State Circuits Conference, February 2001, pp. 402–403.

4. A multigigahertz clocking scheme for the Pentium® 4 microprocessor;Kurd;IEEE Journal of Solid-State Circuits,2001

5. S. Tam et al., Clock generation and distribution of a dual-core xeon processor with 16MB L3 Cache, in: Proceedings of the IEEE International Solid-State Circuits Conference, February 2006, pp. 1512–1521.

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