A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips-Reference-Cited by-同舟云学术

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A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

P Lakshmi Sarvaani¹,A Subba Ramkumar Reddy²,Pudi Vikramkumar¹,M Naga Teja Babu²

Affiliation:

1. IIT Tirupati,India

2. Intel,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181875.pdf?arnumber=10181875

Reference12 articles.

1. Local clock skew minimization using blockage-aware mixed tree-mesh clock network

2. Hybrid Multisource Clock Tree Synthesis

3. A comparative study on multisource clock network synthesis;chen;Proc SASIMI,0

4. Clock Network Synthesis Based on Clock Mesh Technology

5. Clock Tree Skew Minimization with Structured Routing

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

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