Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors
Author:
Affiliation:
1. Xi’an Jiaotong University,School of Microelectronics,Xi’an,China
2. Beijing Institute of Open Source Chip,Beijing,China
3. Peking University,School of Software and Microelectronics,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10661305/10661306/10661311.pdf?arnumber=10661311
Reference11 articles.
1. What’s The Difference Between CTS, Multisource CTS, And Clock Mesh?;Toyama,2012
2. Clock Distribution Architectures: A Comparative Study
3. Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors
4. Zero skew clock routing with minimum wirelength
5. Sizing of clock distribution networks for high performance CPU chips
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