Sizing of clock distribution networks for high performance CPU chips
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Publisher
ACM
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http://xplorestaging.ieee.org/ielx3/3826/11178/00545607.pdf?arnumber=545607
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1. Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18
2. Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-01
3. Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks;Integration;2013-09
4. Revisiting automated physical synthesis of high-performance clock networks;ACM Transactions on Design Automation of Electronic Systems;2013-03
5. Distributed LC Resonant Clock Grid Synthesis;IEEE Transactions on Circuits and Systems I: Regular Papers;2012-11
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