A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability-Reference-Cited by-同舟云学术

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A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability

Published:2013-03 Issue: Volume: Page:
ISSN:
Container-title:International Symposium on Quality Electronic Design (ISQED)
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Author:

Salahuddin S. Muhammad,Hailong Jiao ,Kursun V.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6520923/6523572/06523634.pdf?arnumber=6523634

Cited by 43 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A FinFET-based low-power, stable 8T SRAM cell with high yield;AEU - International Journal of Electronics and Communications;2024-02

2. FinFETs and their Applications;Nanoscale Field Effect Transistors: Emerging Applications;2023-12-19

3. Improved Stability for Robust and Low-Power SRAM Cell using FinFET Technology;Journal of Circuits, Systems and Computers;2023-10-28

4. Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes;2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC);2023-10-16

5. A low-power SRAM design with enhanced stability and I_ON/I_OFF ratio in FinFET technology for wearable device applications;International Journal of Electronics;2023-07-25

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