Author:
Parthasarathy R.S.,Sridhar R.
Cited by
6 articles.
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1. XNOR-XOR based Full Adder Using Double Pass Transistor Logic;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19
2. DPL-based novel CMOS 1-Trit Ternary Full-Adder;International Journal of Electronics;2020-07-09
3. DPL-Based Novel 1-Trit Ternary Half-Subtractor;Lecture Notes in Electrical Engineering;2019-12-17
4. Optimization techniques for FPGA-based wave-pipelined DSP blocks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-07
5. Automating wave-pipelined circuit design;IEEE Design & Test of Computers;2003-11