Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software,Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
4 articles.
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1. WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining;2021 Design, Automation & Test in Europe Conference & Exhibition (DATE);2021-02-01
2. Power-Aware Automated Pipelining of Combinational Circuits;Journal of Low Power Electronics;2015-09-01
3. Power-Aware Automated Pipelining of Combinational Circuits;2014 Fifth International Symposium on Electronic System Design;2014-12
4. EDP optimized synthesis scheme for Boolean read-once functions;International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.;2006