XNOR-XOR based Full Adder Using Double Pass Transistor Logic
Author:
Affiliation:
1. BMS College of Engineering,Department of Electronics and Communication,Bangalore,Karnataka,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10169132/10169913/10169925.pdf?arnumber=10169925
Reference11 articles.
1. A new full-adder design using XNOR-XOR circuit
2. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
3. Double pass-transistor logic for high performance wave pipeline circuits
4. Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
5. Design and analysis four bit hybrid full adder cell using gate diffusion input technique and domino logic
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low Power CMOS based 4-2 Compressor Architecture Using XOR-XNOR and Multiplexers;2024 3rd International Conference on Computational Modelling, Simulation and Optimization (ICCMSO);2024-06-14
2. Implementation of 1-bit Full Adder using Various Low Power Techniques on 45nm Technology;2023 9th International Conference on Signal Processing and Communication (ICSC);2023-12-21
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