Author:
Gotam Sandeep,Kumar Rajeev,Singh Vikram
Cited by
4 articles.
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1. Optimizing Multiplier Performance with Advanced PTL-Based AND Gate and Efficient Full Adder Design;2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC);2024-06-28
2. Specific Design on Arithmetic Circuits with Low Power for VLSI Architectures;International Journal of Advanced Research in Science, Communication and Technology;2024-01-02
3. Energy efficient full adder using mirror circuits;AIP Conference Proceedings;2024
4. XNOR-XOR based Full Adder Using Double Pass Transistor Logic;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19