A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/7066864/07038232.pdf?arnumber=7038232
Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter;Journal of Circuits, Systems and Computers;2024-06-01
2. A D-Band Phased-Array Chain Based on a Tunable Branchline Coupler and a Digitally Controlled Vector Modulator;IEEE Journal of Microwaves;2024-01
3. Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique;International Journal of Circuit Theory and Applications;2023-11-30
4. A random shifting data weighted averaging algorithm for Nyquist-rate DAC;IEICE Electronics Express;2023-10-25
5. A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
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