A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter

Abstract

In this research, we present a 16-bit multi-mode digital-to-analog converter (DAC) with a time-interleaved (TI) structure operating at a frequency of 4 GHz over a bandwidth (BW) of 20 MHz, which is in compliance with the fifth generation (5G) wireless communications. The proposed architecture uses only one clock frequency to generate radio frequency (RF) signals and includes a second-order (2nd-order) delta-sigma modulator (DSM) with a reconfigurable low-pass (LP) mode, band-pass (BP) mode at Fs/4, and high-pass (HP) mode for signal synthesis. To increase the sampling frequency (Fs) of the TI structure, four channels are proposed, each working at a frequency of Fs/4. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. This leads to design simplification, lower power consumption, smaller occupied area, and higher speed. A major challenge in designing this type of structure is the duty-cycle-error (DCE), especially in interleaved mode. In this research, we propose a new solution that solves DCE-related problems without adding digital circuits to the output of the DSM, by adjusting the analog filter circuit. Simulation results in MATLAB show that the value of signal-to-noise and distortion ratio (SNDR) in LP is equal to 106.14 dB, in BP is equal to 107.84 dB, and in HP is equal to 105.34 dB. Compensating for filters increases the spurious-free dynamic range (SFDR) to more than 118 dB.