A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging-Reference-Cited by-同舟云学术

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging

Published:2023-05 Issue:5 Volume:70 Page:1856-1867
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Fu Yushen¹^ORCID,Huang Chengyu¹,Lai Longqiang¹^ORCID,Sun Nan¹,Li Xueqing¹^ORCID,Yang Huazhong¹^ORCID

Affiliation:

1. Department of Electronic Engineering, Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing, China

Funder

NSFC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10109891/10048527.pdf?arnumber=10048527

Reference49 articles.

1. A 16b 6GS/s Nyquist DAC with IMD < ?90dBc up to 1.9 GHz in 16 nm CMOS;lin;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2018

2. A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

3. Order Statistics and Optimal Selection of Unit Elements in DACs to Enhance the Static Linearity

4. Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs

5. Compensation and Calibration Techniques for Current-Steering DACs

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