A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution-Reference-Cited by-同舟云学术

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Published:2017-01 Issue:1 Volume:52 Page:250-260
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sohn Kyomin^ORCID,Yun Won-Joo,Oh Reum,Oh Chi-Sung,Seo Seong-Young,Park Min-Sang,Shin Dong-Hak,Jung Won-Chang,Shin Sang-Hoon,Ryu Je-Min,Yu Hye-Seung,Jung Jae-Hun,Lee Hyunui,Kang Seok-Yong,Sohn Young-Soo,Choi Jung-Hwan,Bae Yong-Cheol,Jang Seong-Jin,Jin Gyoyoung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7811159/07565556.pdf?arnumber=7565556

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