Energy efficient 5 Gb/s baseband transceiver for 3D memory interconnect
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Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s11042-024-19988-x.pdf
Reference32 articles.
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3. Oh K-I et al (2009) A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme. IEEE J Solid-State Circuits 44(8):2222–2232
4. Poulton J, Palmer R, Fuller AM, Greer T, Eyles J, Dally WJ, Horowitz M (2007) A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS. IEEE J Solid-State Circuits 42(12):2745–2757
5. Sohn K et al (2017) A 1.2 v 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution. IEEE J Solid-State Circuits 52(1):250–260. https://doi.org/10.1109/JSSC.2016.2602221
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