A 30-GHz Digital Sub-Sampling Fractional-$N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8910478/08850091.pdf?arnumber=8850091
Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 21.8–41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller;IEEE Transactions on Microwave Theory and Techniques;2024-09
2. A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs;Microelectronics Journal;2024-04
3. A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm;IEEE Journal of Solid-State Circuits;2024-03
4. A 27.2–31.2 GHz 92-fs rms Integrated Jitter, Fractional-N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS;IEEE Transactions on Microwave Theory and Techniques;2023-12
5. A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness;IEEE Journal of Solid-State Circuits;2023-07
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