A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$-Reference-Cited by-同舟云学术

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A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$

Published:2018-04 Issue:4 Volume:53 Page:1006-1015
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Dong Qing^ORCID,Jeloka Supreet^ORCID,Saligane Mehdi^ORCID,Kim Yejoong^ORCID,Kawaminami Masaru,Harada Akihiko,Miyoshi Satoru,Yasuda Makoto,Blaauw David,Sylvester Dennis

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8325040/08172037.pdf?arnumber=8172037

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3. Brain-inspired computing systems: a systematic literature review;The European Physical Journal B;2024-06

4. Impact of Aging and Process Variability on SRAM-Based In-Memory Computing Architectures;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06

5. A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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