A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{\rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques-Reference-Cited by-同舟云学术

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A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{\rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques

Published:2013-10 Issue:10 Volume:48 Page:2558-2569
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chang Meng-Fan,Chen Ming-Pin,Chen Lai-Fu,Yang Shu-Meng,Kuo Yao-Jen,Wu Jui-Jen,Su Hsiu-Yun,Chu Yuan-Hua,Wu Wen-Ching,Yang Tzu-Yi,Yamauchi Hiroyuki

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6605547/06575157.pdf?arnumber=6575157

Cited by 40 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05

4. Reliability improved dual driven feedback 10T SRAM bit cell;Microelectronics Reliability;2022-12

5. An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit;IEEE Journal of Solid-State Circuits;2022-11

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