A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

Author:

Shen YiORCID,Tang XiyuanORCID,Shen LinxiaoORCID,Zhao WendaORCID,Xin Xin,Liu Shubin,Zhu ZhangmingORCID,Sathe Visvesh S.,Sun NanORCID

Funder

National Science Foundation

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs;Journal of Instrumentation;2024-01-01

2. A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier;IEEE Journal of Solid-State Circuits;2023-10

3. A 0.0072-mm2 10-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17

4. Digitalized analog integrated circuits;Fundamental Research;2023-02

5. A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-10

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