A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/4/6392234/06332545.pdf?arnumber=6332545
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1. Design of a very low power 12 bits, 40 MS/s ADC based on a time-interleaved SAR architecture;Journal of Instrumentation;2024-05-01
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4. A Cryo-CMOS PLL for Quantum Computing Applications;IEEE Journal of Solid-State Circuits;2023-05
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