A Cryo-CMOS PLL for Quantum Computing Applications-Reference-Cited by-同舟云学术

A Cryo-CMOS PLL for Quantum Computing Applications

Published:2023-05 Issue:5 Volume:58 Page:1362-1375
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Gong Jiang¹^ORCID,Charbon Edoardo²^ORCID,Sebastiano Fabio¹^ORCID,Babaie Masoud³^ORCID

Affiliation:

1. Department of Quantum and Computer Engineering, Delft University of Technology, Delft, The Netherlands

2. Kavli Institute of Nanoscience, Delft, The Netherlands

3. QuTech, Delft, The Netherlands

Funder

Intel Corporation

Netherlands Organization for Scientific Research

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10107667/09966319.pdf?arnumber=9966319

Reference65 articles.

1. 13.2 A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots

2. A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

3. A 200 dB FoM 4-to-5 GHz cryogenic oscillator with an automatic common-mode resonance calibration for quantum computing applications;gong;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

4. A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier

5. A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

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