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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

  • Published:2017-10 Issue:10 Volume:52 Page:2576-2588
  • ISSN:0018-9200
  • Container-title:IEEE Journal of Solid-State Circuits
  • language:
  • Short-container-title:IEEE J. Solid-State Circuits

Author:

Chan Chi-HangORCID,Zhu YanORCID,Li Cheng,Zhang Wai-Hong,Ho Iok-Meng,Wei Lai,U Seng-Pan,Martins Rui Paulo

Funder

Fundo para o Desenvolvimento das Ciências e da Tecnologia

Research Grants of University of Macau

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 41 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Simulation of 1 0- Bit SAR ADC Using 18nm FinFET Technology;2024 IEEE 14th Symposium on Computer Applications & Industrial Electronics (ISCAIE);2024-05-24

2. A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

3. Design of a 10-BIT 100MSPS Sar ADC;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

4. An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

5. A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator;IEEE Journal of Solid-State Circuits;2023-12
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