Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers
Author:
Funder
Semiconductor Research Corporation
Analog Devices
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8364639/08338365.pdf?arnumber=8338365
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1. A Fractional-N DTC-based ADPLL using path-select multi-delay line TDC and true fractional division technique;Microelectronics Journal;2024-03
2. An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration;IEEE Journal of Solid-State Circuits;2024
3. Design and Analysis of a Fractional Frequency Synthesizer With $<$90-fs Jitter and $<$ $-$103-dBc Spurious Tones Using Digital Spur Cancellation;IEEE Journal of Solid-State Circuits;2024
4. Design of Synthesizable Digital Phase Locked Loops;IPSJ Transactions on System and LSI Design Methodology;2024
5. Design of 2.1-4.8GHz Fractional-N Frequency Divider based on Digital Delta-Sigma Modulator and Clock Distribution Technique;2023 Asia-Pacific Microwave Conference (APMC);2023-12-05
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