Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry-Reference-Cited by-同舟云学术

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

Published:2013-01 Issue:1 Volume:48 Page:46-65
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Okada Kenichi,Kondou Keitarou,Miyahara Masaya,Shinagawa Masashi,Asada Hiroki,Minami Ryo,Yamaguchi Tatsuya,Musa Ahmed,Tsukui Yuuki,Asakura Yasuo,Tamonoki Shinya,Yamagishi Hiroyuki,Hino Yasufumi,Sato Takahiro,Sakaguchi Hironori,Shimasaki Naoki,Ito Toshihiko,Takeuchi Yasuaki,Li Ning,Bu Qinghong,Murakami Rui,Bunsen Keigo,Matsushita Kota,Noda Makoto,Matsuzawa Akira

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6399535/06339016.pdf?arnumber=6339016

Cited by 95 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 60-GHz Highly Reused Joint Radar– Communication Transceiver With Reconfigurable Dual-Mode Gilbert Cells in 65-nm CMOS;IEEE Microwave and Wireless Technology Letters;2024-06

2. A Fully Integrated QPSK/16-QAM $D$-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces;IEEE Journal of Solid-State Circuits;2024

3. High-Power 150/245-GHz Fundamental Oscillators With 12.1/$-$2.54-dBm Peak Output Power for Phased Array Transceivers;IEEE Journal of Solid-State Circuits;2024

4. A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology;IEICE Electronics Express;2023-10-25

5. A Study of Phase-Adjusting Architectures for Low-Phase-Noise Quadrature Voltage-Controlled Oscillators;IEICE Transactions on Electronics;2023-02-01